兼容MCS-52单片机的PWM控制器设计
兼容MCS-VII单片机的PWM控制器设计
作者:胡阅历,王伟微电子研究开发中心
摘要:在本文中,我们就PWM控制技术作I.些讨论.脉宽调制技术是I.种将开关频率固定,通过控制开关信号的占空比,来调节负载两端直流平均电压的方法.该技术应用被广泛于包括电动机控制.温度控制和压力控制等场合.
关键字:PWM技术;频率;电机控制
导言
脉宽调制技术是I.种将开关频率固定,通过控制开关信号的占空比,来调节负载两端直流平均电压的方法.该技术应用被广泛于包括电动机控制.温度控制和压力控制等场合.在电机系统中的应用,如图I.所示,通过调整电源开关的占空比,来控制电机的速度,如图II所示,平均电压通过改变占空比来控制电机的速度(在图中D=tI./T),这样当电机的电源打开时,它的速度加快,相反,当电源关闭时,速度下降.
图I.PWM控制框图图II电压的电枢和占空比之间的关系
所以,通过定期地调整时间的开通和关断来控制电机的转速:这儿有III种方法可以完成占空比的调整(I.)固定脉宽,调整频率实现;(II)通过同时调整频率和脉宽;(III)固定频率,调整脉宽实现
I.般情况下,有如下IV种方法可以产生PWM信号:(I.)由独立的逻辑元件组成的装置产生,这种是原始的方法,现在已被淘汰;(II)通过软件产生,这种方法需要CPU持续操作指令来控制I/O口,以致于CPU不能做其他任何事.所以,这种方法也渐渐被淘汰;(III)通过ASIC产生,这种方法减少了CPU的负担,能稳定工作,通常还具有几种功能,如过电流保护.死区时间调整等等;现在这种方法已经被广泛用于许多场合;(IV)通过单片机的PWM功能模块产生,通过单片机嵌入PWM功能模块和初始化功能,当需要改变占空比时,除了CPU控制外,单片机的PWM引脚也可以自动产生PWM输出信号.这种 *好棒文|www.hbsrm.com +Q: ￥3^5`1^9`1^6^0`7^2$
方法将在文章中实行.
在本文中,我们提议在VIII0VII单片机里嵌入I.个PWM模块.该PWM模块支持PWM脉冲信号,通过初始化控制寄存器和占空比寄存器,和刚才上面提到III种方法来调整占空比,并且可以通过多种操作模式来增加用户灵活性.
以下这部分说明了PWM模块和基本功能模块的结构.第III部分描述两种操作模式.这部分还讲述了,利用实验和仿真结果验证系统的正常运行.通过操作模式,PWM模块产生I.个或更多的占空比可以自动调整的脉宽调制信号.
在单片机上执行PWM模块
PWM模块的概述
PWM模块的框图如图III所示,从图中,可以很清楚得看到整个模块有两部分组成:PWM信号产生器和带有通道选择逻辑的死区时间产生器.PWM功能可以由用户通过执行I.些指令使PWM模块初始化,从而启动.特别是在电源和电机控制中得到应用支持.
I..直流电机
II.持续电源供电
PWM模块也有以下特征:
I..两个PWM输出信号以互补或独立的方式运行
II.带有互补模式的硬件死区时间发生器
III.占空比更新设置应立刻或与PWM同步
图IIIPWM模块的结构
PWM结构的详细组成
PWM发生器
两输出PWM发生器的结构如图IV所示,该结构是能产生脉宽调制信号的I.VI位计数器.该系统信号由IV分频或XII分频的时钟信号合成,时钟信号的频率可通过对特殊寄存器PWMCON中的PWM0发生器的位TIIIM或PWMI.发生器的位TIVM的值进行设置而调整,如图IV所示:对于PWM0发生器,当TIIIM位被设置为零时,I.VI位计数器的时钟信号频率将被默认设置为IV分频,当TIIIM位被设置为I.时,时钟信号的频率将设置为XII分频;这同样适用于PWMI.发生器.在PWMCON中的其它位的定义,详见表I.
图IVPWMCON的位的位置
表I.PWMCON的位的定义
通道选择逻辑
如图V所示,通道选择逻辑在互补模式中很有用.从这幅图中可以清楚得看出,信号CP和CPWM控制PWMI.和PWML的来源.这两个控制信号的详细情况将在第III部分讲述,死区时间发生器的结构也将在第V部分互补模式的连续性中讲述.
图V通道选择逻辑表
操作模式和仿真结果
这种设计有两种操作模式:独立模式和互补模式.通过设置如图IV中PWMCON寄存器中相应的位CPWM,用户可以选择两种操作模式中的I.种.当CPWM位被设置为0时,PWM模块将以独立模式工作,否则,PWM模块将以互补模式工作.在本节的下文中,这两种操作模式将被分别详细讲述,并且通过从EDA平台得到的的PWM模块的仿真结果来验证这种设计.
独立PWM输出模块
独立PWM输出模块对于驱动负载很有用,如图VI所示.当在PWMCON寄存器中相应的CP位设置为0时,I.个特定的PWM输出处于独立输出模式.在这种情况下,两通道的PWM输出是相互独立的.引脚PWM0/PWMH口的信号是从PWM0发生器产生的,而引脚PWMI./PWML口的信号是从PWMI.发生器产生的.通道选择逻辑单独完成情况,如图VI所示.PWM的I/O口通过默认复位设置为独立模式,但死区时间发生器不能在独立模式下工作.仿真结果如图VI所示.TrIV和TrIII位被用来控制PWM0和PWMI. *好棒文|www.hbsrm.com +Q: ￥3^5`1^9`1^6^0`7^2$
发生器.实际上,从图看,单片机的PI.^V/PI.^IV口被用做控制PWMH/PWML或是I.般的I/O口.
图VI独立模式下的PWM波形
互补PWM输出模式
互补输出模式可以用于驱动逆变器负载,如图VII所示.这种逆变器拓扑是典型的直流应用.在互补输出模式中,PWM的两个输出不能同时用.PWM通道和输出口都是通过通道选择逻辑对内部进行配置的,如图VII所示.死区时间可以选择在两端输出端的开关元件未工作时插入.
图VIIPWM互补输出的典型电路
PWM的I/O引脚通过设置寄存器PWMCON中适当的CPWM位选择互补模式,在这种情况下,PSEL有效.当PSEL设置为0时,PWMH和PWML的信号将来自PWM0发生器,这时来自PWMI.发生器的信号是没用的,而当PSEL设置为I.时,PWMH和PWML的信号将来自PWMI.发生器,这时来自PWM0发生器的信号是没用的.在互补模式时产生PWM输出信号的过程中,死区时间将被在以下这部分讲述.
死区时间控制
当PWM的I/O引脚在互补输出模式运行时,死区时间是自动启用的.因为电源输出元件不能瞬间开关,在互补模式下,I.个PWM输出信号的关闭与其它晶体管打开之间要I.定的时间,两输出的PWM模块有I.个可以对死区时间编程的VIII位寄存器.
该对互补输出的PWM模块具有有I.个用于产生死区时间的VIII位计数器.如图VIII所示,死区时间单元有I.个上升沿和下降沿探测器,而这个探测器与PWM发生器产生的PWM信号连接.当到达PWM边沿时,死区时间被载入计时器,根据是否是上升沿或下降沿,该对互补输出的转换中的I.个被延迟,直到计数器降为0.PWM输出对应的死区时间表,如图VIIIa所示:
图VIIIa死区时间单元模块图
图VIIIb互补模式的PWM输出波形
ATVIIIIXSVII是I.种低功耗,高性能,在系统内部具有VIIIK字节可编程存储的VIII位微控制器.该元件用Atmel公司的高密度存储器技术制造,与标准工业VIII0CVI.指令集和引脚兼容.片上Flash允许程序存储器在系统或传统的内存编程.Atmel公司的ATVIIIIXSVII是I.个功能强大的单片机,它为许多嵌入式控制应用提供了高度灵活性和具有成本效益的解决方案.ATVIIIIXSVII提供以下标准功能:VIIIK字节的闪存,IIVVI字节的RAM,IIIII个I/O线,看门狗定时器,两个数据指针,III个I.VI位定时器/计数器,I.个VI向量的II级中断,I.个全双工串行口,片内振荡器和时钟电路.此外,ATVIIIIXSVII可以设计静态逻辑操作到零频率并且支持两种软件可选的节电模式.空闲模式时停止CPU,但是RAM,定时器/计数器,串口和中断系统继续运行.掉电模式保存RAM的内容,但关闭晶振,禁用芯片的所有其他功能,直到下I.个中断或硬件复位.
引脚说明
VCC:电源电压
GND:接地
Port0:端口0口是I.个VIII位开路双向I/O口.作为I.个输出端口,每个引脚可驱动VIII个逻辑电平输入.当端口0引脚写入高电平I.时,该引脚可作为高阻抗输入.在访问外部程序和数据存储器时,端口0也可以配置为低位地址/数据总线.在这种模式下,端口0具有内部上拉电阻.端口0在Flash编程时接收代码字节,并且验证程序时输出代码字节.验证程序时外部必须加上拉电阻.
PortI.:端口I.是I.个具有内部上拉电阻的VIII位双向I/O口.端口I.输出缓冲器可以驱动IV个逻辑电平输入.当端口I.引脚写入高电平I.时,他们内部上拉电阻拉高,并且可作为输入端口.作为输入端口,由于内部上拉电阻,外部将被拉低,输出电流(IIL).此外,PI..0和PI..I.可以配置为定时器/计数器II的外部计数输入(PI..0/TII)和定时器/计数器II的触发输入(PI..I./TIIEX),分别,如下表I.所示.端口I.在Flash编程和校验时也可以接收低位地址字节.
表I.端口I.的特殊功能
PortPinAlternateFunctions
PI..0TII(externalcountinputtoTimer/CounterII),clock-out
PI..I.TIIEX(Timer/CounterIIcapture/reloadtriggeranddirectioncontrol)
PI..VMOSI(usedforIn-SystemProgramming)
PI..VIMISO(usedforIn-SystemProgramming)
PI..VIISCK(usedforIn-SystemProgramming)
PortII:端口II是I.个具有内部上拉电阻的VIII位双向I/O口.端口II输出缓冲器可以驱动IV个逻辑电平输入.当端口II引脚写入高电平I.时,他们内部上拉电阻拉高,可作为输入使用.作为输入,由于内部上拉电阻,外部将被拉低,输出电流(IIL).端口II存放的高位地址字节在获取外部程序存储器和在访问外部数据存储器使用I.VI位地址(MOVX@DPTR).在这种应用中,当端口II写入高电平I.时使用大的内部上拉电阻.在访问外部数据存储器使用VIII位地址(MOVX@RI),端口II发出特殊功能寄存器中的内容.端口II在flash编程和校验时也将接收高位地址位和I.些控制信号.
端口III:端口III是I.个具有内部上拉电阻的VIII位双向I/O口.端口III输出缓冲器可以驱动IV个逻辑电平输入.当端口III引脚写入高电平I.时,他们内部上拉电阻拉高,可作为输入使用.作为输入,由于内部上拉电阻,外部将被拉低,输出电流(IIL).端口III接收I.些控制信号对Flash进行编程和验证.端口III也作为ATVIIIIXSVII特殊功能,如以下表II所示.
表II端口III的特殊功能
PortPinAlternateFunctions
PIII.0RXD(serialinputport)
PIII.I.TXD(serialoutputport)
PIII.II(externalinterrupt0)
PIII.III(externalinterruptI.)
PIII.IVT0(timer0externalinput)
PIII.VTI.(timerI.externalinput)
PIII.VI(externaldatamemorywritestrobe)
PIII.VII(externaldatamemoryreadstrobe)
复位:复位输入.当晶振运行复位元件时,在两个时间周期内,该引脚保持高电平.看门狗超时后IXVIII个振荡器周期,该引脚驱动高电平.这个DISRTO位AUXRSFR(地址VIIIEH)可以用来禁用此功能.
ALE/:地址锁存器(ALE)是I.个用于在访问外部存储器时锁存地址的低字节的输出脉冲.该引脚还可以在Flash编程中用于输入编程脉冲(PROG).在正常运行,ALE以I./VI晶振的频率为恒定速率发射,可用于定时或外部时钟的用途.但是请注意,I.个ALE脉冲是在每次访问外部数据存储器时跳过.如果需要,可以通过将特殊寄存器中的地址VIIIEH位置0来禁用ALE操作.随着禁止位被设定,ALE只有在执行MOVX或MOVC指令时是激活的.否则,引脚电平渐渐拉高.如果微控制器处于外部执行模式,设置的ALE禁止位无影响.
:程序存储使能()是读选通到外部程序存储器.当ATVIIIIXSVII从外部程序存储器执行代码,每个机器周期被激活两次,除了在每次访问外部数据存储器时,两个程序存储使能激活被跳过.
/VPP:外部访问允许.为了使设备从开始0000H到FFFFH的外部程序存储器位置获取代码,EA必引脚必须接地,以使设备从外部程序存储器0000H开始执行到FFFFH的取码.但请注意,如果锁定位I.编程,EA引脚需要将内部锁存复位.当执行内部程序时,EA引脚需要接电源.该引脚在Flash编程也将得到I.IIV使能电压(VPP).
XTALI.:晶振输入和内部时钟工作电路的输入.
XTALII:晶振输出.
程序存储器
如果EA引脚接地,所有的程序获取都指向外部存储器.在ATVIIIIXSVII,如果EA引脚接电源,程序获取地址0000H通过I.FFFH是针对内部存储器,并且获取的地址II000H通过FFFFH是外部存储器.
数据存储器
ATVIIIIXSVII实现了IIVVI字节的片上RAM.片上I.IIVIII字节占用并行地址空间的特殊功能寄存器.这意味着,片上I.IIVIII字节具有相同的地址作为特殊功能寄存器的空间而从特殊功能寄存器物理空间上分开.当I.个指令访问内部位置上述地址VIIFH,指令中使用的寻址模式指定CPU访问内存或特殊功能寄存器空间的I.IIVIII字节.使用直接寻址指令访问特殊功能寄存器空间.例如,下面的直接寻址指令访问特殊寄存器的地址0A0H(即PII口).MOV0A0H,#data.使用间接寻址访问片上I.IIVIII字节的RAM指令.例如,下面的间接寻址指令,其中R0包含0A0H,访问的数据字节地址0A0H,而不是为PII(其地址0A0H).movR0,#data.请注意,堆栈操作是间接寻址的例子,所以数据RAM的片上I.IIVIII字节可以作为堆栈空间
看门狗定时器
看门狗定时器在这里是作为CPU可能会受到软件冷门恢复方法.看门狗定时器由I.IV位计数器和看门狗定时器复位(WDTRST)特殊功能寄存器组成的.看门狗定时器默认退出复位时禁用.为了激活看门狗定时器,用户必须依次向看门狗定时器复位寄存器写入0I.EH和0EI.H(特殊功能寄存器地址:0AVIH).当看门狗定时器激活后,当晶振运行时,它将在每个机器周期增加.看门狗定时器超时时间依赖于外部时钟频率.除了复位(无论是硬件复位或复位WDT溢出)没有其他办法禁用看门狗.当看门狗过流时,它将驱动复位引脚输出复位高脉冲.
InPower-downmodetheoscillatorstops,whichmeanstheWDTalsostops.WhileinPower-downmode,theuserdoesnotneedtoservicetheWDT.TherearetwomethodsofexitingPower-downmode:byahardwareresetorviaalevel-activatedexternalinterruptwhichisenabledpriortoenteringPower-downmode.WhenPower-downisexitedwithhardwarereset,servicingtheWDTshouldoccurasitnormallydoeswhenevertheATVIIIIXSVIIisreset.ExitingPower-downwithaninterruptissignificantlydifferent.Theinterruptisheldlowlongenoughfortheoscillatortostabilize.Whentheinterruptisbroughthigh,theinterruptisserviced.TopreventtheWDTfromresettingthedevicewhiletheinterruptpinisheldlow,theWDTisnotstarteduntiltheinterruptispulledhigh.ItissuggestedthattheWDTberesetduringtheinterruptservicefortheinterruptusedtoexitPower-downmode.ToensurethattheWDTdoesnotoverflowwithinafewstatesofexitingPower-down,itisbesttoresettheWDTjustbeforeenteringPower-downmode.BeforegoingintotheIDLEmode,theWDIDLEbitinSFRAUXRisusedtodeterminewhethertheWDTcontinuestocountifenabled.TheWDTkeepscountingduringIDLE(WDIDLEbit=0)asthedefaultstate.TopreventtheWDTfromresettingtheATVIIIIXSVIIwhileinIDLEmode,theusershouldalwayssetupatimerthatwillperiodicallyexitIDLE,servicetheWDT,andreenterIDLEmode.WithWDIDLEbitenabled,theWDTwillstoptocountinIDLEmodeandresumesthecountuponexitfromIDLE.
在掉电模式下,晶振停止,这意味着看门狗也停止了.在掉电模式下,用户不需要服务的看门狗定时器.退出掉电模式的方法有两种:由硬件复位或通过I.个电平触发的外部中断进入掉电模式启动之前.当通过硬件复位退出掉电模式,因为ATVIIIIXSVII单片机复位,看门狗I.般不会发生.为了防止看门狗因为设备复位而中断,中断引脚需要保持低电平,看门狗未启动之前,中断电平引脚被拉高.建议利用中断服务退出掉电模式时,看门狗复位.为了确保看门狗定时器退出掉电模式不会溢出,最好在刚刚进入掉电模式时,复位看门狗.在进入空闲模式时,SFRAUXR的WDIDLE位用来决定看门狗定时器是否继续计数.如果启用,看门狗定时器继续计数.在空闲模式时WDIDLE位=0是作为默认的状态.随着WDIDLE位启用,看门狗将停止,并从空闲模式退出重新开始计数.
定时器0和I.
定时器0和定时器I.在ATVIIIIXSVII的操作方式同定时器0和定时器I.在ATVIIIIXCVI.单片机ATVIIIIXCVII中的操作方式相同.
定时器II
TimerIIisaI.VI-bitTimer/Counterthatcanoperateaseitheratimeroraneventcounter.ThetypeofoperationisselectedbybitC/intheSFRTIICON.TimerIIhasthreeoperatingmodes:capture,auto-reload(upordowncounting),andbaudrategenerator.ThemodesareselectedbybitsinTIICON,asshowninTableVI-I..TimerIIconsistsoftwoVIII-bitregisters,THIIandTLII.IntheTimerfunction,theTLIIregisterisincrementedeverymachinecycle.SinceamachinecycleconsistsofI.IIoscillatorperiods,thecountrateisI./I.IIoftheoscil-latorfrequency.
定时器II是I.个I.VI位定时器/计数器,可以作为I.个定时器或计数器.运行类型由特殊寄存器TIICON中的位C/TII选择.定时器II有III种工作模式:捕捉,自动重载(向上或向下计数)和波特率发生器.模式由TIICON中的位选择,如表III.定时器II包含两个VIII位寄存器,分别是THII和TLII.在定时器功能中,TLII寄存器在每个机器周期递增.由于I.个机器周期包含I.II个时钟周期,所以计数率是I./I.II的晶振频率
表III定时器II的操作模式
RCLK+TCLKCP/TRIIMODE
00I.I.VI-bitAuto-reload
0I.I.I.VI-bitCapture
I.XI.BaudRateGenerator
XX0(Off)
在计数器功能中,该寄存器在其相应的外部输入引脚TII中I.到0的范围中递增响应.在这个功能中,外部输入对每个机器周期进行采样.当采样结果显示在这个周期高,在下I.个周期低时,计数递增.由于两个机器周期(IIIV个振荡周期)都必须有I.个I.-0的过渡,最大的计数率为I.／IIIV的晶振频率.
中断
TheATVIIIIXSVIIhasatotalofsixinterruptvectors:twoexternalinterrupts(and),threetimerinterrupts(Timers0,I.,andII),andtheserialportinterrupt.EachoftheseinterruptsourcescanbeindividuallyenabledordisabledbysettingorclearingabitinSpecialFunctionRegisterIE.IEalsocontainsaglobaldisablebit,EA,whichdisablesallinterruptsatonce.NotethatbitpositionIE.VIisunimplemented.UsersoftwareshouldnotwriteaI.tothisbitposition,sinceitmaybeusedinfutureATVIIIIXproducts.TimerIIinterruptisgeneratedbythelogicalORofbitsTFIIandEXFIIinregisterTIICON.Nei-theroftheseflagsisclearedbyhardwarewhentheserviceroutineisvectoredto.Infact,theserviceroutinemayhavetodeterminewhetheritwasTFIIorEXFIIthatgeneratedtheinterrupt,andthatbitwillhavetobeclearedinsoftware.TheTimer0andTimerI.flags,TF0andTFI.,aresetatSVPIIofthecycleinwhichthetimersoverflow.Thevaluesarethenpolledbythecircuitryinthenextcycle.However,theTimerIIflag,TFII,issetatSIIPIIandispolledinthesamecycleinwhichthetimeroverflows.
ATVIIIIXSVII共有VI个中断向量:两个外部中断,III个定时器中断(定时器0,I.,和II),和I.个串行中断.每个中断源都可以单独启用或禁用设置或清除特殊功能寄存器IE.IE还包含了I.个全局禁止位EA,它可I.次性禁止所有中断.需要注意的是位的位置IEVI未实现.用户软件不应写高电平到该位,因为它可能会在将来来ATVIIIIX产品中使用.定时器II中断由位TFII和EXFII在寄存器TIICON的逻辑或产生.当中断服务程序被引用时,这些逻辑标志由硬件清零.事实上,中断服务程序需要确定是TFII还是EXFII位产生中断,产生中断的这I.点必须用软件清零.定时器0和定时器I.的标志,TF0和TFI.,在本周期中设置为SVPII,定时器溢出.其值在下I.个周期中循环.然而,定时器II的标志,TFII,设置为sIIpII,并在同I.周期中循环,定时器溢出.
晶振的特性
XTALI.andXTALIIaretheinputandoutput,respectively,ofaninvertingamplifierthatcanbeconfiguredforuseasanon-chiposcillator.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTALIIshouldbeleftunconnectedwhileXTALI.isdriven,.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclock-ingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.
XTALI.和XTALII分别是可以配置为I.个片上晶振反相放大器的输入和输出.无论是石英晶体或陶瓷谐振器可以使用.当驱动外部时钟源器件时,XTALII应悬空而XTALI.驱动.因为输入到内部时钟电路的输入通过I.个两分频触发器,所以对外部时钟信号的占空比没有任何要求.
Power-downMode
掉电模式
InthePower-downmode,theoscillatorisstopped,andtheinstructionthatinvokesPower-downisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthePower-downmodeisterminated.ExitfromPower-downmodecanbeinitiatedeitherbyahardwareresetorbyanenabledexternalinterrupt.ResetredefinestheSFRsbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.
在掉电模式下,晶振停止工作,并且调用掉电指令是最后I.条指令.片上RAM和特殊功能寄存器的值保持不变,直到掉电模式终止.退出掉电模式可以通过硬件复位或外部中断启动.复位后将重新定义功能寄存器但不改变片内RAM.复位需要等待VCC恢复到正常工作水平,并且必须保持足够长时间,使晶振重新启动并稳定下来.
IdleMod
空闲模式
Inidlemode,theCPUputsitselftosleepwhilealltheon-chipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregis-tersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.Notethatwhenidlemodeisterminatedbyahardwarereset,thedevicenormallyresumespro-gramexecutionfromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.Toeliminatethepossibilityofanunexpectedwritetoaportpinwhenidlemodeisterminatedbyareset,theinstructionfollowingtheonethatinvokesidlemodeshouldnotwritetoaportpinortoexternalmemory.
在空闲模式下,CPU进入睡眠状态,而所有片上外设仍然很活跃.这种模式由软件方式调用.在这种模式下的片内RAM和所有特殊功能寄存器的内容保持不变.空闲模式可以被任何使能的中断或硬件复位终止.请注意,当空闲模式被硬件复位终止,恢复设备正常程序从停止处执行,最多两个机器周期之前重置内部算法控制.在这种情况下片上硬件禁止访问内部RAM,但不阻止访问端口引脚.当空闲模式被复位终止,为了消除I.个意外的写入的端口引脚,下I.个调用空闲模式的指令不应该写I.个端口引脚或外部存储器.
总结:
本文,我们设计了VIII位兼容VIII0VII单片机的PWM模块,这种设计能产生两通道带有两种运行模式的可编程周期PWM信号,即可插入死区时间的独立模式和互补模式.EDA平台的仿真结果已证明了它的正确性和有用性.
附件II:外文原文(复印件)
DesignofPWMControllerinaMCS-VIICompatibleMCU
Author:Yue-LiHu,WeiWangMicroelectronicResearch&DevelopmentCenter
CampusP.O.B.IIIII.,I.IVIXYanchangRd,ShanghaiII000VIIII,China
Abstract:Inthispaper,wewilltalksomethingaboutPWMtechnology.PWMtechnologyisakindofvoltageregulationmethodbycontrollingtheswitchfrequencyofDCpowerwithfixedvoltagetomodifythetwo-endvoltageofload.Thistechnologycanbeusedforavarietyofapplicationsincludingmotorcontrol,temperaturecontrolandpressurecontrolandsoon.Thistechniquewillbewidelyusedinmotorcontrol.
Keywords:PWMtechnology;frequency;motorcontrol
Introduction
PWMtechnologyisakindofvoltageregulationmethodbycontrollingtheswitchfrequencyofDCpowerwithfixedvoltagetomodifythetwo-endvoltageofload.Thistechnologycanbeusedforavarietyofapplicationsincludingmotorcontrol,temperaturecontrolandpressurecontrolandsoon.InthemotorcontrolsystemshownasFig.I.,throughadjustingthedutycycleofpowerswitch,thespeedofmotorcanbecontrolled.AsshowninFig.II,underthecontrolofPWMsignal,theaverageofvoltagethatcontrolsthespeedofmotorchangeswithDuty-cycle(D=tI./TinthisFigure),thusthemotorspeedcanbeincreasedwhenmotorpowerturnon,decreasedwhenpowerturnoff.
Fig.I.:TheRelationshipbetweenVoltageofArmatureandFig.IIArchitectureofPWMModule
Therefore,themotorspeedcanbecontrolledwithregularlyadjustingthetimeofturn-onandturn-off.Therearethreemethodscouldachievetheadjustmentofdutycycle:(I.)Adjustfrequencywithfixedpulse-width.(II)Adjustbothfrequencyandpulse-width.(III)Adjustpulse-widthwithfixedfrequency.
Generally,therearefourmethodstogeneratethePWMsignalsasthefollowing:(I.)Generatedbythedevicecomposedofseparatelogiccomponents.Thismethodistheoriginalmethodwhichnowhasbeendiscarded.(II)Generatedbysoftware.ThismethodneedCPUtocontinuouslyoperateinstructionstocontrolI/OpinsforgeneratingPWMoutputsignals,sothatCPUcannotdoanythingother.Therefore,themethodalsohasbeendiscardedgradually.(III)GeneratedbyASIC.TheASICmakesadecreaseofCPUburdenandsteadyworkgenerallyhasseveralfunctionssuchasover-currentprotection,dead-timeadjustmentandsoon.Thenthemethodhasbeenwidelyusedinmanykindsofoccasionnow.(IV)GeneratedbyPWMfunctionmoduleofMCU.ThroughembeddingPWMfunctionmoduleinMCUandinitializingthefunction,PWMpinsofMCUcanalsoautomaticallygeneratePWMoutsignalswithoutCPUcontrollingonlywhenneedtochangeduty-cycle.Itisthemethodthatwillbeimplementedinthispaper.
Inthispaper,weproposeaPWMmoduleembeddedinaVIII0VIImicrocontroller.ThePWMmodulecansupportPWMpulsesignalsbyinitializingthecontrolregisterandduty-cycleregisterwiththreemethodsjustmentionedabovetoadjustthedutycycleandseveraloperationmodestoaddflexibilityforuser.
ThefollowingsectionexplainsthearchitectureofthePWMmoduleandthearchitecturesofbasicfunctionalblocks.SectionIIIdescribestwooperationmodes.Experimentalandsimulationresultsverifyingpropersystemoperationarealsoshowninthatsection.Dependingonmodeofoperation,thePWMmodulecreatesoneormorepulse-widthmodulatedsignals,whosedutyratioscanbeindependentlyadjusted.
ImplementationofPWMmoduleinMCU
OverviewofthePWMmodule
AblockdiagramofPWMmoduleisshowninFig.III.Itisclearlyfromthediagramthatthewholemoduleiscomposedoftwosections:PWMsignalgeneratoranddead-timegeneratorwithchannelselectlogic.ThePWMfunctioncanbestartedbytheuserthroughimplementingsomeinstructionsforinitializingthePWMmodule.Inparticular,thefollowingpowerandmotioncontrolapplicationsaresupported:
?DCMotor
?UninterruptablelPowerSupply(UPS)
·ThePWMmodulealsohasthefollowingfeatures:
?TwoPWMsignaloutputswithcomplementaryorindependentoperation
?Hardwaredead-timegeneratorsforcomplementarymode
?DutycycleupdatesareconfigurabletobeimmediatedorsynchronizedtothePWM
Fig.IIIArchitectureofPWMModule
Detailsofthearchitecture
PMWgenerator
ThearchitectureoftheII-outputPWMgeneratorshowninFig.IVisbasedonaI.VI-bitresolutioncounterwhichcreatesapulse-widthmodulatedsignal.ThesystemissynthesizedbyasystemclocksignalwhosefrequencycanbedividedbyIVtimesorI.IItimesthroughsettingthevalueofTIIIMforPWM0orTIVMforPWMI.inthespecialregisterPWMCONasshowninFig.IV.ToPWM0generator,theclocktoI.VI-bitcounterwillbepre-dividedbyIVtimesbydefaultwhenTIIIMissettozero.AndtheclockwillbedividedbyI.IItimeswhenTIIIMissettoI..ThisisalsotrueforPWMI..TheotherbitsinPWMCONareexplainedindetailinTableI..
Fig.IVBitMappingofPWMCON
TableI.:TheBitDefinitioninPWMCON
Channel-selectlogic
ThefollowFig.Vshowsthechannel-selectlogicwhichisusefulinComplementaryMode.Fromthisdiagram,itiscleartoknowthatsignalCPandCPWMcontrolthesourceofPWMHandPWML.AndthedetailsaboutthetwocontrolsignalswillbediscussedinthesectionIII,andthearchitectureofdead-timegeneratorwillalsobediscussedinsectionVforthecontinuityofComplementaryMode.
Fig.VDiagramofChannel-selectLogic
OperationModeandSimulationResults
Thedesignhastwooperationmodes:IndependentModeandComplimentaryMode.BysettingthecorrespondingbitCPWMinregisterPWMCONshowninFig.VIusercanselectoneofthetwooperationmodes.WhenCPWMissettozero,PWMmodulewillworkinIndependentMode,whereas,PWMmodulewillworkinComplimentaryMode.Inthefollowingofthissection,thetwooperationmodewillbeexplainedrespectivelyindetailandthesimulationresultsofthePWMmodulefromtheSynoposysVCSEDAplatformwhichverifythedesignwillalsobeshown.
IndependentPWMOutputMode
AnIndependentPWMOutputmodeisusefulfordrivingloadssuchastheoneshowninFigureVI.AparticularPWMoutputisintheIndependentOutputmodewhenthecorrespondingCPbitinthePWMCONregisterissettozero.Inthiscase,two-channelPWMoutputsareindependentofeachother.ThesignalonpinPWM0/PWMHisfromPWM0generator,andthesignalonpinPWMI./PWMLisfromPWM0generator.Theseparatecaseisachievedbythechannel-selectlogicshowninFig.VI.ThePWMI/Opinsaresettoindependentmodebydefaultuponadvicereset.Thedead-timegeneratorisdisabledintheIndependentmode.ThesimulationresultisshowninFigureVIasthefollowingFig.VITrIVandtrIIIarerunbitstoPWM0andPWMI.,respectively.Actually,fromthisdiagram,PinPI.[V]/PI.[IV]ofMCUisusedforPWMH/PWMLornormalI/O,alternatively.
FigVItheWaveformofPWMOutputsinIndependentMode
ComplementaryPWMOutputMode
TheComplementaryOutputmodeisusedtodriveinverterloadssimilartotheoneshowninFigureVII.ThisinvertertopologyistypicalforDCapplications.InComplementaryOutputMode,thepairofPWMoutputscannotbeactivesimultaneously.ThePWMchannelandoutputpinpairareinternallyconfiguredthroughchannel-selectlogicasshowninFigureVII.Adead-timemaybeoptionallyinsertedduringdeviceswitchingwherebothoutputsareinactiveforashortperiod.
FigVII:TypicalLoadforComplementaryPWMOutputs
TheComplementarymodeisselectedforPWMI/OpinpairbysettingtheappropriateCPWMbitinPWMCON.Inthiscase,PSELisineffect.PWMHandPWMLwillcomefromPWM0generatorwhenPSELissettozero,whenthesignalsfromPWMI.generatorisuseless,whereasPWMHandPWMLwillcomefromPWMI.generatorwhenPSELissettoI.,whenthesignalsfromPWM0generatorisuseless.IntheprocessofproducingthePWMoutputsinComplementaryMode,thedead-timewillbeinsertedtobediscussedinthefollowingsection.
Dead-timeControl
Dead-timegenerationisautomaticallyenabledwhenPWMI/OpinpairisoperatingintheComplementaryOutputmode.Becausethepoweroutputdevicescannotswitchinstantaneously,someamountoftimemustbeprovidedbetweentheturn-offeventofonePWMoutputinacomplementarypairandtheturn-oneventoftheothertransistor.TheII-outputPWMmodulehasoneprogrammabledead-timewithVIII-bitregister.ThecomplementaryoutputpairforthePWMmodulehasanVIII-bitdowncounterthatisusedtoproducethedead-timeinsertion.AsshowninFigureVIII,thedeadtimeunithasarisingandfallingedgedetectorconnectedtoPWMsignalfromoneofPWMgenerator.ThedeadtimesisloadedintothetimeronthedetectedPWMedgeevent.Dependingonwhethertheedgeisrisingorfalling,oneofthetransitionsonthecomplementaryoutputsisdelayeduntilthetimercountsdowntozero.AtimingdiagramindicatingthedeadtimeinsertionforthepairofPWMoutputsisshowninFigureVIIIa.
FigVIIIaDead-timeUnitBlockDiagram
Fig.VIIIbtheWaveformsofPWMOutputsinComplementaryMode
TheATVIIIIXSVIIisalow-power,high-performanceCMOSVIII-bitmicrocontrollerwithVIIIKbytesofin-systemprogrammableFlashmemory.ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindus-try-standardVIII0CVI.instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememorypro-grammer.BycombiningaversatileVIII-bitCPUwithin-systemprogrammableFlashonamonolithicchip,theAtmelATVIIIIXSVIIisapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.TheATVIIIIXSVIIprovidesthefollowingstandardfeatures:VIIIKbytesofFlash,IIVVIbytesofRAM,IIIIII/Olines,Watchdogtimer,twodatapointers,threeI.VI-bittimer/counters,asix-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theATVIIIIXSVIIisdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcon-tentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextinterruptorhardwarereset.
PinDescription
VCC:Supplyvoltage.
GND:Ground.
Port0:Port0isanVIII-bitopendrainbidirectionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.WhenI.sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpull-ups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesdur-ingprogramverification.Externalpull-upsarerequiredduringprogramverification.
PortI.:PortI.isanVIII-bitbidirectionalI/Oportwithinternalpull-ups.ThePortI.outputbufferscansink/sourcefourTTLinputs.WhenI.sarewrittentoPortI.pins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,PortI.pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Inaddition,PI..0andPI..I.canbeconfiguredtobethetimer/counterIIexternalcountinput(PI..0/TII)andthetimer/counterIItriggerinput(PI..I./TIIEX),respectively,asshowninthefollow-ingtableI..PortI.alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.
TableI.ThesecondfunctionofthePI.port
PortPinAlternateFunctions
PI..0TII(externalcountinputtoTimer/CounterII),clock-out
PI..I.TIIEX(Timer/CounterIIcapture/reloadtriggeranddirectioncontrol)
PI..VMOSI(usedforIn-SystemProgramming)
PI..VIMISO(usedforIn-SystemProgramming)
PI..VIISCK(usedforIn-SystemProgramming)
PortII:PortIIisanVIII-bitbidirectionalI/Oportwithinternalpull-ups.ThePortIIoutputbufferscansink/sourcefourTTLinputs.WhenI.sarewrittentoPortIIpins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,PortIIpinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.PortIIemitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryanddur-ingaccessestoexternaldatamemorythatuseI.VI-bitaddresses(MOVX@DPTR).Inthisapplication,PortIIusesstronginternalpull-upswhenemittingI.s.DuringaccessestoexternaldatamemorythatuseVIII-bitaddresses(MOVX@RI),PortIIemitsthecontentsofthePIISpecialFunctionRegister.PortIIalsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogram-mingandverification.
PortIII:PortIIIisanVIII-bitbidirectionalI/Oportwithinternalpull-ups.ThePortIIIoutputbufferscansink/sourcefourTTLinputs.WhenI.sarewrittentoPortIIIpins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,PortIIIpinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepull-ups.PortIIIreceivessomecontrolsignalsforFlashprogrammingandverification.PortIIIalsoservesthefunctionsofvariousspecialfeaturesoftheATVIIIIXSVII,asshowninthefol-lowingtableII.
TableIIThesecondfunctionofthePIIIport
PortPinAlternateFunctions
PIII.0RXD(serialinputport)
PIII.I.TXD(serialoutputport)
PIII.II(externalinterrupt0)
PIII.III(externalinterruptI.)
PIII.IVT0(timer0externalinput)
PIII.VTI.(timerI.externalinput)
PIII.VI(externaldatamemorywritestrobe)
PIII.VII(externaldatamemoryreadstrobe)
RST:Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.ThispindriveshighforIXVIIIoscillatorperiodsaftertheWatchdogtimesout.TheDISRTObitinSFRAUXR(addressVIIIEH)canbeusedtodisablethisfeature.InthedefaultstateofbitDISRTO,theRESETHIGHoutfeatureisenabled.
ALE/:AddressLatchEnable(ALE)isanoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput()duringFlashprogramming.Innormaloperation,ALEisemittedataconstantrateofI./VItheoscillatorfrequencyandmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippeddur-ingeachaccesstoexternaldatamemory.Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocationVIIIEH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.
:ProgramStoreEnable()isthereadstrobetoexternalprogrammemory.WhentheATVIIIIXSVIIisexecutingcodefromexternalprogrammemory,isactivatedtwiceeachmachinecycle,exceptthattwoactivationsareskippedduringeachaccesstoexter-naldatamemory.
/VPP:ExternalAccessEnable.mustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbitI.isprogrammed,willbeinternallylatchedonreset.shouldbestrappedtoVCCforinternalprogramexecutions.ThispinalsoreceivestheI.II-voltprogrammingenablevoltage(VPP)duringFlashprogramming.
XTALI.:Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.
XTALII:Outputfromtheinvertingoscillatoramplifier.
ProgramMemory
IfthepinisconnectedtoGND,allprogramfetchesaredirectedtoexternalmemory.OntheATVIIIIXSVII,ifisconnectedtoVCC,programfetchestoaddresses0000HthroughI.FFFHaredirectedtointernalmemoryandfetchestoaddressesII000HthroughFFFFHaretoexternalmemory.
DataMemory
TheATVIIIIXSVIIimplementsIIVVIbytesofon-chipRAM.TheupperI.IIVIIIbytesoccupyaparalleladdressspacetotheSpecialFunctionRegisters.ThismeansthattheupperI.IIVIIIbyteshavethesameaddressesastheSFRspacebutarephysicallyseparatefromSFRspace.WhenaninstructionaccessesaninternallocationaboveaddressVIIFH,theaddressmodeusedintheinstructionspecifieswhethertheCPUaccessestheupperI.IIVIIIbytesofRAMortheSFRspace.InstructionswhichusedirectaddressingaccesstheSFRspace.Forexample,thefollowingdirectaddressinginstructionaccessestheSFRatlocation0A0H(whichisPII).MOV0A0H,#data.InstructionsthatuseindirectaddressingaccesstheupperI.IIVIIIbytesofRAM.Forexample,thefollowingindirectaddressinginstruction,whereR0contains0A0H,accessesthedatabyteataddress0A0H,ratherthanPII(whoseaddressis0A0H).MOV@R0,#data.Notethatstackoperationsareexamplesofindirectaddressing,sotheupperI.IIVIIIbytesofdataRAMareavailableasstackspace.
WatchdogTimer
TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsets.TheWDTconsistsofaI.IV-bitcounterandtheWatchdogTimerReset(WDTRST)SFR.TheWDTisdefaultedtodisablefromexitingreset.ToenabletheWDT,ausermustwrite0I.EHand0EI.HinsequencetotheWDTRSTregister(SFRlocation0AVIH).WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.TheWDTtimeoutperiodisdependentontheexternalclockfrequency.ThereisnowaytodisabletheWDTexceptthroughreset(eitherhardwareresetorWDToverflowreset).WhenWDTover-flows,itwilldriveanoutputRESETHIGHpulseattheRSTpin.
InPower-downmodetheoscillatorstops,whichmeanstheWDTalsostops.WhileinPower-downmode,theuserdoesnotneedtoservicetheWDT.TherearetwomethodsofexitingPower-downmode:byahardwareresetorviaalevel-activatedexternalinterruptwhichisenabledpriortoenteringPower-downmode.WhenPower-downisexitedwithhardwarereset,servicingtheWDTshouldoccurasitnormallydoeswhenevertheATVIIIIXSVIIisreset.ExitingPower-downwithaninterruptissignificantlydifferent.Theinterruptisheldlowlongenoughfortheoscillatortostabilize.Whentheinterruptisbroughthigh,theinterruptisserviced.TopreventtheWDTfromresettingthedevicewhiletheinterruptpinisheldlow,theWDTisnotstarteduntiltheinterruptispulledhigh.ItissuggestedthattheWDTberesetduringtheinterruptservicefortheinterruptusedtoexitPower-downmode.ToensurethattheWDTdoesnotoverflowwithinafewstatesofexitingPower-down,itisbesttoresettheWDTjustbeforeenteringPower-downmode.BeforegoingintotheIDLEmode,theWDIDLEbitinSFRAUXRisusedtodeterminewhethertheWDTcontinuestocountifenabled.TheWDTkeepscountingduringIDLE(WDIDLEbit=0)asthedefaultstate.TopreventtheWDTfromresettingtheATVIIIIXSVIIwhileinIDLEmode,theusershouldalwayssetupatimerthatwillperiodicallyexitIDLE,servicetheWDT,andreenterIDLEmode.WithWDIDLEbitenabled,theWDTwillstoptocountinIDLEmodeandresumesthecountuponexitfromIDLE.
Timer0andI.
Timer0andTimerI.intheATVIIIIXSVIIoperatethesamewayasTimer0andTimerI.intheATVIIIIXCVI.andATVIIIIXCVII.Forfurtherinformationonthetimers’operation,pleaseclickonthedocumentlinkbelow:
http://www.atmel.com/dyn/resources/prod_documents/DOCIVIIII.VI.PDF
TimerII
TimerIIisaI.VI-bitTimer/Counterthatcanoperateaseitheratimeroraneventcounter.ThetypeofoperationisselectedbybitC/intheSFRTIICON.TimerIIhasthreeoperatingmodes:capture,auto-reload(upordowncounting),andbaudrategenerator.ThemodesareselectedbybitsinTIICON,asshowninTableVI-I..TimerIIconsistsoftwoVIII-bitregisters,THIIandTLII.IntheTimerfunction,theTLIIregisterisincrementedeverymachinecycle.SinceamachinecycleconsistsofI.IIoscillatorperiods,thecountrateisI./I.IIoftheoscil-latorfrequency.
TableIIITimerIIOperatingModes
RCLK+TCLKCP/TRIIMODE
00I.I.VI-bitAuto-reload
0I.I.I.VI-bitCapture
I.XI.BaudRateGenerator
XX0(Off)
IntheCounterfunction,theregisterisincrementedinresponsetoaI.-to-0transitionatitscorre-spondingexternalinputpin,TII.Inthisfunction,theexternalinputissampledduringSVPIIofeverymachinecycle.Whenthesamplesshowahighinonecycleandalowinthenextcycle,thecountisincremented.ThenewcountvalueappearsintheregisterduringSIIIPI.ofthecyclefollowingtheoneinwhichthetransitionwasdetected.Sincetwomachinecycles(IIIVoscillatorperiods)arerequiredtorecognizeaI.-to-0transition,themaximumcountrateisI./IIIVoftheoscillatorfrequency.Toensurethatagivenlevelissampledatleastoncebeforeitchanges,thelevelshouldbeheldforatleastonefullmachinecycle.
Interrupts
TheATVIIIIXSVIIhasatotalofsixinterruptvectors:twoexternalinterrupts(and),threetimerinterrupts(Timers0,I.,andII),andtheserialportinterrupt.EachoftheseinterruptsourcescanbeindividuallyenabledordisabledbysettingorclearingabitinSpecialFunctionRegisterIE.IEalsocontainsaglobaldisablebit,EA,whichdisablesallinterruptsatonce.NotethatbitpositionIE.VIisunimplemented.UsersoftwareshouldnotwriteaI.tothisbitposition,sinceitmaybeusedinfutureATVIIIIXproducts.TimerIIinterruptisgeneratedbythelogicalORofbitsTFIIandEXFIIinregisterTIICON.Nei-theroftheseflagsisclearedbyhardwarewhentheserviceroutineisvectoredto.Infact,theserviceroutinemayhavetodeterminewhetheritwasTFIIorEXFIIthatgeneratedtheinterrupt,andthatbitwillhavetobeclearedinsoftware.TheTimer0andTimerI.flags,TF0andTFI.,aresetatSVPIIofthecycleinwhichthetimersoverflow.Thevaluesarethenpolledbythecircuitryinthenextcycle.However,theTimerIIflag,TFII,issetatSIIPIIandispolledinthesamecycleinwhichthetimeroverflows.
OscillatorCharacteristics
XTALI.andXTALIIaretheinputandoutput,respectively,ofaninvertingamplifierthatcanbeconfiguredforuseasanon-chiposcillator.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTALIIshouldbeleftunconnectedwhileXTALI.isdriven,.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclock-ingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.
Power-downMode
InthePower-downmode,theoscillatorisstopped,andtheinstructionthatinvokesPower-downisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthePower-downmodeisterminated.ExitfromPower-downmodecanbeinitiatedeitherbyahardwareresetorbyanenabledexternalinterrupt.ResetredefinestheSFRsbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.
IdleMod
Inidlemode,theCPUputsitselftosleepwhilealltheon-chipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregis-tersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.Notethatwhenidlemodeisterminatedbyahardwarereset,thedevicenormallyresumespro-gramexecutionfromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.Toeliminatethepossibilityofanunexpectedwritetoaportpinwhenidlemodeisterminatedbyareset,theinstructionfollowingtheonethatinvokesidlemodeshouldnotwritetoaportpinortoexternalmemory.
Conclusions
Inthispaper,wehavedesignedPWMmodulebasedonanVIII-bitMCUcompatiblewithVIII0VIIfamily.ThedesigncangenerateII-channelprogrammableperiodicPWMsignalswithtwooperationmode,IndependentModeandComplementaryModeinwhichdead-timewillbeinserted.ThesimulationresultsontheEDAplatformhaveprovenitscorrectnessandusefulness.
作者:胡阅历,王伟微电子研究开发中心
摘要:在本文中,我们就PWM控制技术作I.些讨论.脉宽调制技术是I.种将开关频率固定,通过控制开关信号的占空比,来调节负载两端直流平均电压的方法.该技术应用被广泛于包括电动机控制.温度控制和压力控制等场合.
关键字:PWM技术;频率;电机控制
导言
脉宽调制技术是I.种将开关频率固定,通过控制开关信号的占空比,来调节负载两端直流平均电压的方法.该技术应用被广泛于包括电动机控制.温度控制和压力控制等场合.在电机系统中的应用,如图I.所示,通过调整电源开关的占空比,来控制电机的速度,如图II所示,平均电压通过改变占空比来控制电机的速度(在图中D=tI./T),这样当电机的电源打开时,它的速度加快,相反,当电源关闭时,速度下降.
图I.PWM控制框图图II电压的电枢和占空比之间的关系
所以,通过定期地调整时间的开通和关断来控制电机的转速:这儿有III种方法可以完成占空比的调整(I.)固定脉宽,调整频率实现;(II)通过同时调整频率和脉宽;(III)固定频率,调整脉宽实现
I.般情况下,有如下IV种方法可以产生PWM信号:(I.)由独立的逻辑元件组成的装置产生,这种是原始的方法,现在已被淘汰;(II)通过软件产生,这种方法需要CPU持续操作指令来控制I/O口,以致于CPU不能做其他任何事.所以,这种方法也渐渐被淘汰;(III)通过ASIC产生,这种方法减少了CPU的负担,能稳定工作,通常还具有几种功能,如过电流保护.死区时间调整等等;现在这种方法已经被广泛用于许多场合;(IV)通过单片机的PWM功能模块产生,通过单片机嵌入PWM功能模块和初始化功能,当需要改变占空比时,除了CPU控制外,单片机的PWM引脚也可以自动产生PWM输出信号.这种 *好棒文|www.hbsrm.com +Q: ￥3^5`1^9`1^6^0`7^2$
方法将在文章中实行.
在本文中,我们提议在VIII0VII单片机里嵌入I.个PWM模块.该PWM模块支持PWM脉冲信号,通过初始化控制寄存器和占空比寄存器,和刚才上面提到III种方法来调整占空比,并且可以通过多种操作模式来增加用户灵活性.
以下这部分说明了PWM模块和基本功能模块的结构.第III部分描述两种操作模式.这部分还讲述了,利用实验和仿真结果验证系统的正常运行.通过操作模式,PWM模块产生I.个或更多的占空比可以自动调整的脉宽调制信号.
在单片机上执行PWM模块
PWM模块的概述
PWM模块的框图如图III所示,从图中,可以很清楚得看到整个模块有两部分组成:PWM信号产生器和带有通道选择逻辑的死区时间产生器.PWM功能可以由用户通过执行I.些指令使PWM模块初始化,从而启动.特别是在电源和电机控制中得到应用支持.
I..直流电机
II.持续电源供电
PWM模块也有以下特征:
I..两个PWM输出信号以互补或独立的方式运行
II.带有互补模式的硬件死区时间发生器
III.占空比更新设置应立刻或与PWM同步
图IIIPWM模块的结构
PWM结构的详细组成
PWM发生器
两输出PWM发生器的结构如图IV所示,该结构是能产生脉宽调制信号的I.VI位计数器.该系统信号由IV分频或XII分频的时钟信号合成,时钟信号的频率可通过对特殊寄存器PWMCON中的PWM0发生器的位TIIIM或PWMI.发生器的位TIVM的值进行设置而调整,如图IV所示:对于PWM0发生器,当TIIIM位被设置为零时,I.VI位计数器的时钟信号频率将被默认设置为IV分频,当TIIIM位被设置为I.时,时钟信号的频率将设置为XII分频;这同样适用于PWMI.发生器.在PWMCON中的其它位的定义,详见表I.
图IVPWMCON的位的位置
表I.PWMCON的位的定义
通道选择逻辑
如图V所示,通道选择逻辑在互补模式中很有用.从这幅图中可以清楚得看出,信号CP和CPWM控制PWMI.和PWML的来源.这两个控制信号的详细情况将在第III部分讲述,死区时间发生器的结构也将在第V部分互补模式的连续性中讲述.
图V通道选择逻辑表
操作模式和仿真结果
这种设计有两种操作模式:独立模式和互补模式.通过设置如图IV中PWMCON寄存器中相应的位CPWM,用户可以选择两种操作模式中的I.种.当CPWM位被设置为0时,PWM模块将以独立模式工作,否则,PWM模块将以互补模式工作.在本节的下文中,这两种操作模式将被分别详细讲述,并且通过从EDA平台得到的的PWM模块的仿真结果来验证这种设计.
独立PWM输出模块
独立PWM输出模块对于驱动负载很有用,如图VI所示.当在PWMCON寄存器中相应的CP位设置为0时,I.个特定的PWM输出处于独立输出模式.在这种情况下,两通道的PWM输出是相互独立的.引脚PWM0/PWMH口的信号是从PWM0发生器产生的,而引脚PWMI./PWML口的信号是从PWMI.发生器产生的.通道选择逻辑单独完成情况,如图VI所示.PWM的I/O口通过默认复位设置为独立模式,但死区时间发生器不能在独立模式下工作.仿真结果如图VI所示.TrIV和TrIII位被用来控制PWM0和PWMI. *好棒文|www.hbsrm.com +Q: ￥3^5`1^9`1^6^0`7^2$
发生器.实际上,从图看,单片机的PI.^V/PI.^IV口被用做控制PWMH/PWML或是I.般的I/O口.
图VI独立模式下的PWM波形
互补PWM输出模式
互补输出模式可以用于驱动逆变器负载,如图VII所示.这种逆变器拓扑是典型的直流应用.在互补输出模式中,PWM的两个输出不能同时用.PWM通道和输出口都是通过通道选择逻辑对内部进行配置的,如图VII所示.死区时间可以选择在两端输出端的开关元件未工作时插入.
图VIIPWM互补输出的典型电路
PWM的I/O引脚通过设置寄存器PWMCON中适当的CPWM位选择互补模式,在这种情况下,PSEL有效.当PSEL设置为0时,PWMH和PWML的信号将来自PWM0发生器,这时来自PWMI.发生器的信号是没用的,而当PSEL设置为I.时,PWMH和PWML的信号将来自PWMI.发生器,这时来自PWM0发生器的信号是没用的.在互补模式时产生PWM输出信号的过程中,死区时间将被在以下这部分讲述.
死区时间控制
当PWM的I/O引脚在互补输出模式运行时,死区时间是自动启用的.因为电源输出元件不能瞬间开关,在互补模式下,I.个PWM输出信号的关闭与其它晶体管打开之间要I.定的时间,两输出的PWM模块有I.个可以对死区时间编程的VIII位寄存器.
该对互补输出的PWM模块具有有I.个用于产生死区时间的VIII位计数器.如图VIII所示,死区时间单元有I.个上升沿和下降沿探测器,而这个探测器与PWM发生器产生的PWM信号连接.当到达PWM边沿时,死区时间被载入计时器,根据是否是上升沿或下降沿,该对互补输出的转换中的I.个被延迟,直到计数器降为0.PWM输出对应的死区时间表,如图VIIIa所示:
图VIIIa死区时间单元模块图
图VIIIb互补模式的PWM输出波形
ATVIIIIXSVII是I.种低功耗,高性能,在系统内部具有VIIIK字节可编程存储的VIII位微控制器.该元件用Atmel公司的高密度存储器技术制造,与标准工业VIII0CVI.指令集和引脚兼容.片上Flash允许程序存储器在系统或传统的内存编程.Atmel公司的ATVIIIIXSVII是I.个功能强大的单片机,它为许多嵌入式控制应用提供了高度灵活性和具有成本效益的解决方案.ATVIIIIXSVII提供以下标准功能:VIIIK字节的闪存,IIVVI字节的RAM,IIIII个I/O线,看门狗定时器,两个数据指针,III个I.VI位定时器/计数器,I.个VI向量的II级中断,I.个全双工串行口,片内振荡器和时钟电路.此外,ATVIIIIXSVII可以设计静态逻辑操作到零频率并且支持两种软件可选的节电模式.空闲模式时停止CPU,但是RAM,定时器/计数器,串口和中断系统继续运行.掉电模式保存RAM的内容,但关闭晶振,禁用芯片的所有其他功能,直到下I.个中断或硬件复位.
引脚说明
VCC:电源电压
GND:接地
Port0:端口0口是I.个VIII位开路双向I/O口.作为I.个输出端口,每个引脚可驱动VIII个逻辑电平输入.当端口0引脚写入高电平I.时,该引脚可作为高阻抗输入.在访问外部程序和数据存储器时,端口0也可以配置为低位地址/数据总线.在这种模式下,端口0具有内部上拉电阻.端口0在Flash编程时接收代码字节,并且验证程序时输出代码字节.验证程序时外部必须加上拉电阻.
PortI.:端口I.是I.个具有内部上拉电阻的VIII位双向I/O口.端口I.输出缓冲器可以驱动IV个逻辑电平输入.当端口I.引脚写入高电平I.时,他们内部上拉电阻拉高,并且可作为输入端口.作为输入端口,由于内部上拉电阻,外部将被拉低,输出电流(IIL).此外,PI..0和PI..I.可以配置为定时器/计数器II的外部计数输入(PI..0/TII)和定时器/计数器II的触发输入(PI..I./TIIEX),分别,如下表I.所示.端口I.在Flash编程和校验时也可以接收低位地址字节.
表I.端口I.的特殊功能
PortPinAlternateFunctions
PI..0TII(externalcountinputtoTimer/CounterII),clock-out
PI..I.TIIEX(Timer/CounterIIcapture/reloadtriggeranddirectioncontrol)
PI..VMOSI(usedforIn-SystemProgramming)
PI..VIMISO(usedforIn-SystemProgramming)
PI..VIISCK(usedforIn-SystemProgramming)
PortII:端口II是I.个具有内部上拉电阻的VIII位双向I/O口.端口II输出缓冲器可以驱动IV个逻辑电平输入.当端口II引脚写入高电平I.时,他们内部上拉电阻拉高,可作为输入使用.作为输入,由于内部上拉电阻,外部将被拉低,输出电流(IIL).端口II存放的高位地址字节在获取外部程序存储器和在访问外部数据存储器使用I.VI位地址(MOVX@DPTR).在这种应用中,当端口II写入高电平I.时使用大的内部上拉电阻.在访问外部数据存储器使用VIII位地址(MOVX@RI),端口II发出特殊功能寄存器中的内容.端口II在flash编程和校验时也将接收高位地址位和I.些控制信号.
端口III:端口III是I.个具有内部上拉电阻的VIII位双向I/O口.端口III输出缓冲器可以驱动IV个逻辑电平输入.当端口III引脚写入高电平I.时,他们内部上拉电阻拉高,可作为输入使用.作为输入,由于内部上拉电阻,外部将被拉低,输出电流(IIL).端口III接收I.些控制信号对Flash进行编程和验证.端口III也作为ATVIIIIXSVII特殊功能,如以下表II所示.
表II端口III的特殊功能
PortPinAlternateFunctions
PIII.0RXD(serialinputport)
PIII.I.TXD(serialoutputport)
PIII.II(externalinterrupt0)
PIII.III(externalinterruptI.)
PIII.IVT0(timer0externalinput)
PIII.VTI.(timerI.externalinput)
PIII.VI(externaldatamemorywritestrobe)
PIII.VII(externaldatamemoryreadstrobe)
复位:复位输入.当晶振运行复位元件时,在两个时间周期内,该引脚保持高电平.看门狗超时后IXVIII个振荡器周期,该引脚驱动高电平.这个DISRTO位AUXRSFR(地址VIIIEH)可以用来禁用此功能.
ALE/:地址锁存器(ALE)是I.个用于在访问外部存储器时锁存地址的低字节的输出脉冲.该引脚还可以在Flash编程中用于输入编程脉冲(PROG).在正常运行,ALE以I./VI晶振的频率为恒定速率发射,可用于定时或外部时钟的用途.但是请注意,I.个ALE脉冲是在每次访问外部数据存储器时跳过.如果需要,可以通过将特殊寄存器中的地址VIIIEH位置0来禁用ALE操作.随着禁止位被设定,ALE只有在执行MOVX或MOVC指令时是激活的.否则,引脚电平渐渐拉高.如果微控制器处于外部执行模式,设置的ALE禁止位无影响.
:程序存储使能()是读选通到外部程序存储器.当ATVIIIIXSVII从外部程序存储器执行代码,每个机器周期被激活两次,除了在每次访问外部数据存储器时,两个程序存储使能激活被跳过.
/VPP:外部访问允许.为了使设备从开始0000H到FFFFH的外部程序存储器位置获取代码,EA必引脚必须接地,以使设备从外部程序存储器0000H开始执行到FFFFH的取码.但请注意,如果锁定位I.编程,EA引脚需要将内部锁存复位.当执行内部程序时,EA引脚需要接电源.该引脚在Flash编程也将得到I.IIV使能电压(VPP).
XTALI.:晶振输入和内部时钟工作电路的输入.
XTALII:晶振输出.
程序存储器
如果EA引脚接地,所有的程序获取都指向外部存储器.在ATVIIIIXSVII,如果EA引脚接电源,程序获取地址0000H通过I.FFFH是针对内部存储器,并且获取的地址II000H通过FFFFH是外部存储器.
数据存储器
ATVIIIIXSVII实现了IIVVI字节的片上RAM.片上I.IIVIII字节占用并行地址空间的特殊功能寄存器.这意味着,片上I.IIVIII字节具有相同的地址作为特殊功能寄存器的空间而从特殊功能寄存器物理空间上分开.当I.个指令访问内部位置上述地址VIIFH,指令中使用的寻址模式指定CPU访问内存或特殊功能寄存器空间的I.IIVIII字节.使用直接寻址指令访问特殊功能寄存器空间.例如,下面的直接寻址指令访问特殊寄存器的地址0A0H(即PII口).MOV0A0H,#data.使用间接寻址访问片上I.IIVIII字节的RAM指令.例如,下面的间接寻址指令,其中R0包含0A0H,访问的数据字节地址0A0H,而不是为PII(其地址0A0H).movR0,#data.请注意,堆栈操作是间接寻址的例子,所以数据RAM的片上I.IIVIII字节可以作为堆栈空间
看门狗定时器
看门狗定时器在这里是作为CPU可能会受到软件冷门恢复方法.看门狗定时器由I.IV位计数器和看门狗定时器复位(WDTRST)特殊功能寄存器组成的.看门狗定时器默认退出复位时禁用.为了激活看门狗定时器,用户必须依次向看门狗定时器复位寄存器写入0I.EH和0EI.H(特殊功能寄存器地址:0AVIH).当看门狗定时器激活后,当晶振运行时,它将在每个机器周期增加.看门狗定时器超时时间依赖于外部时钟频率.除了复位(无论是硬件复位或复位WDT溢出)没有其他办法禁用看门狗.当看门狗过流时,它将驱动复位引脚输出复位高脉冲.
InPower-downmodetheoscillatorstops,whichmeanstheWDTalsostops.WhileinPower-downmode,theuserdoesnotneedtoservicetheWDT.TherearetwomethodsofexitingPower-downmode:byahardwareresetorviaalevel-activatedexternalinterruptwhichisenabledpriortoenteringPower-downmode.WhenPower-downisexitedwithhardwarereset,servicingtheWDTshouldoccurasitnormallydoeswhenevertheATVIIIIXSVIIisreset.ExitingPower-downwithaninterruptissignificantlydifferent.Theinterruptisheldlowlongenoughfortheoscillatortostabilize.Whentheinterruptisbroughthigh,theinterruptisserviced.TopreventtheWDTfromresettingthedevicewhiletheinterruptpinisheldlow,theWDTisnotstarteduntiltheinterruptispulledhigh.ItissuggestedthattheWDTberesetduringtheinterruptservicefortheinterruptusedtoexitPower-downmode.ToensurethattheWDTdoesnotoverflowwithinafewstatesofexitingPower-down,itisbesttoresettheWDTjustbeforeenteringPower-downmode.BeforegoingintotheIDLEmode,theWDIDLEbitinSFRAUXRisusedtodeterminewhethertheWDTcontinuestocountifenabled.TheWDTkeepscountingduringIDLE(WDIDLEbit=0)asthedefaultstate.TopreventtheWDTfromresettingtheATVIIIIXSVIIwhileinIDLEmode,theusershouldalwayssetupatimerthatwillperiodicallyexitIDLE,servicetheWDT,andreenterIDLEmode.WithWDIDLEbitenabled,theWDTwillstoptocountinIDLEmodeandresumesthecountuponexitfromIDLE.
在掉电模式下,晶振停止,这意味着看门狗也停止了.在掉电模式下,用户不需要服务的看门狗定时器.退出掉电模式的方法有两种:由硬件复位或通过I.个电平触发的外部中断进入掉电模式启动之前.当通过硬件复位退出掉电模式,因为ATVIIIIXSVII单片机复位,看门狗I.般不会发生.为了防止看门狗因为设备复位而中断,中断引脚需要保持低电平,看门狗未启动之前,中断电平引脚被拉高.建议利用中断服务退出掉电模式时,看门狗复位.为了确保看门狗定时器退出掉电模式不会溢出,最好在刚刚进入掉电模式时,复位看门狗.在进入空闲模式时,SFRAUXR的WDIDLE位用来决定看门狗定时器是否继续计数.如果启用,看门狗定时器继续计数.在空闲模式时WDIDLE位=0是作为默认的状态.随着WDIDLE位启用,看门狗将停止,并从空闲模式退出重新开始计数.
定时器0和I.
定时器0和定时器I.在ATVIIIIXSVII的操作方式同定时器0和定时器I.在ATVIIIIXCVI.单片机ATVIIIIXCVII中的操作方式相同.
定时器II
TimerIIisaI.VI-bitTimer/Counterthatcanoperateaseitheratimeroraneventcounter.ThetypeofoperationisselectedbybitC/intheSFRTIICON.TimerIIhasthreeoperatingmodes:capture,auto-reload(upordowncounting),andbaudrategenerator.ThemodesareselectedbybitsinTIICON,asshowninTableVI-I..TimerIIconsistsoftwoVIII-bitregisters,THIIandTLII.IntheTimerfunction,theTLIIregisterisincrementedeverymachinecycle.SinceamachinecycleconsistsofI.IIoscillatorperiods,thecountrateisI./I.IIoftheoscil-latorfrequency.
定时器II是I.个I.VI位定时器/计数器,可以作为I.个定时器或计数器.运行类型由特殊寄存器TIICON中的位C/TII选择.定时器II有III种工作模式:捕捉,自动重载(向上或向下计数)和波特率发生器.模式由TIICON中的位选择,如表III.定时器II包含两个VIII位寄存器,分别是THII和TLII.在定时器功能中,TLII寄存器在每个机器周期递增.由于I.个机器周期包含I.II个时钟周期,所以计数率是I./I.II的晶振频率
表III定时器II的操作模式
RCLK+TCLKCP/TRIIMODE
00I.I.VI-bitAuto-reload
0I.I.I.VI-bitCapture
I.XI.BaudRateGenerator
XX0(Off)
在计数器功能中,该寄存器在其相应的外部输入引脚TII中I.到0的范围中递增响应.在这个功能中,外部输入对每个机器周期进行采样.当采样结果显示在这个周期高,在下I.个周期低时,计数递增.由于两个机器周期(IIIV个振荡周期)都必须有I.个I.-0的过渡,最大的计数率为I.／IIIV的晶振频率.
中断
TheATVIIIIXSVIIhasatotalofsixinterruptvectors:twoexternalinterrupts(and),threetimerinterrupts(Timers0,I.,andII),andtheserialportinterrupt.EachoftheseinterruptsourcescanbeindividuallyenabledordisabledbysettingorclearingabitinSpecialFunctionRegisterIE.IEalsocontainsaglobaldisablebit,EA,whichdisablesallinterruptsatonce.NotethatbitpositionIE.VIisunimplemented.UsersoftwareshouldnotwriteaI.tothisbitposition,sinceitmaybeusedinfutureATVIIIIXproducts.TimerIIinterruptisgeneratedbythelogicalORofbitsTFIIandEXFIIinregisterTIICON.Nei-theroftheseflagsisclearedbyhardwarewhentheserviceroutineisvectoredto.Infact,theserviceroutinemayhavetodeterminewhetheritwasTFIIorEXFIIthatgeneratedtheinterrupt,andthatbitwillhavetobeclearedinsoftware.TheTimer0andTimerI.flags,TF0andTFI.,aresetatSVPIIofthecycleinwhichthetimersoverflow.Thevaluesarethenpolledbythecircuitryinthenextcycle.However,theTimerIIflag,TFII,issetatSIIPIIandispolledinthesamecycleinwhichthetimeroverflows.
ATVIIIIXSVII共有VI个中断向量:两个外部中断,III个定时器中断(定时器0,I.,和II),和I.个串行中断.每个中断源都可以单独启用或禁用设置或清除特殊功能寄存器IE.IE还包含了I.个全局禁止位EA,它可I.次性禁止所有中断.需要注意的是位的位置IEVI未实现.用户软件不应写高电平到该位,因为它可能会在将来来ATVIIIIX产品中使用.定时器II中断由位TFII和EXFII在寄存器TIICON的逻辑或产生.当中断服务程序被引用时,这些逻辑标志由硬件清零.事实上,中断服务程序需要确定是TFII还是EXFII位产生中断,产生中断的这I.点必须用软件清零.定时器0和定时器I.的标志,TF0和TFI.,在本周期中设置为SVPII,定时器溢出.其值在下I.个周期中循环.然而,定时器II的标志,TFII,设置为sIIpII,并在同I.周期中循环,定时器溢出.
晶振的特性
XTALI.andXTALIIaretheinputandoutput,respectively,ofaninvertingamplifierthatcanbeconfiguredforuseasanon-chiposcillator.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTALIIshouldbeleftunconnectedwhileXTALI.isdriven,.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclock-ingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.
XTALI.和XTALII分别是可以配置为I.个片上晶振反相放大器的输入和输出.无论是石英晶体或陶瓷谐振器可以使用.当驱动外部时钟源器件时,XTALII应悬空而XTALI.驱动.因为输入到内部时钟电路的输入通过I.个两分频触发器,所以对外部时钟信号的占空比没有任何要求.
Power-downMode
掉电模式
InthePower-downmode,theoscillatorisstopped,andtheinstructionthatinvokesPower-downisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthePower-downmodeisterminated.ExitfromPower-downmodecanbeinitiatedeitherbyahardwareresetorbyanenabledexternalinterrupt.ResetredefinestheSFRsbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.
在掉电模式下,晶振停止工作,并且调用掉电指令是最后I.条指令.片上RAM和特殊功能寄存器的值保持不变,直到掉电模式终止.退出掉电模式可以通过硬件复位或外部中断启动.复位后将重新定义功能寄存器但不改变片内RAM.复位需要等待VCC恢复到正常工作水平,并且必须保持足够长时间,使晶振重新启动并稳定下来.
IdleMod
空闲模式
Inidlemode,theCPUputsitselftosleepwhilealltheon-chipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregis-tersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.Notethatwhenidlemodeisterminatedbyahardwarereset,thedevicenormallyresumespro-gramexecutionfromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.Toeliminatethepossibilityofanunexpectedwritetoaportpinwhenidlemodeisterminatedbyareset,theinstructionfollowingtheonethatinvokesidlemodeshouldnotwritetoaportpinortoexternalmemory.
在空闲模式下,CPU进入睡眠状态,而所有片上外设仍然很活跃.这种模式由软件方式调用.在这种模式下的片内RAM和所有特殊功能寄存器的内容保持不变.空闲模式可以被任何使能的中断或硬件复位终止.请注意,当空闲模式被硬件复位终止,恢复设备正常程序从停止处执行,最多两个机器周期之前重置内部算法控制.在这种情况下片上硬件禁止访问内部RAM,但不阻止访问端口引脚.当空闲模式被复位终止,为了消除I.个意外的写入的端口引脚,下I.个调用空闲模式的指令不应该写I.个端口引脚或外部存储器.
总结:
本文,我们设计了VIII位兼容VIII0VII单片机的PWM模块,这种设计能产生两通道带有两种运行模式的可编程周期PWM信号,即可插入死区时间的独立模式和互补模式.EDA平台的仿真结果已证明了它的正确性和有用性.
附件II:外文原文(复印件)
DesignofPWMControllerinaMCS-VIICompatibleMCU
Author:Yue-LiHu,WeiWangMicroelectronicResearch&DevelopmentCenter
CampusP.O.B.IIIII.,I.IVIXYanchangRd,ShanghaiII000VIIII,China
Abstract:Inthispaper,wewilltalksomethingaboutPWMtechnology.PWMtechnologyisakindofvoltageregulationmethodbycontrollingtheswitchfrequencyofDCpowerwithfixedvoltagetomodifythetwo-endvoltageofload.Thistechnologycanbeusedforavarietyofapplicationsincludingmotorcontrol,temperaturecontrolandpressurecontrolandsoon.Thistechniquewillbewidelyusedinmotorcontrol.
Keywords:PWMtechnology;frequency;motorcontrol
Introduction
PWMtechnologyisakindofvoltageregulationmethodbycontrollingtheswitchfrequencyofDCpowerwithfixedvoltagetomodifythetwo-endvoltageofload.Thistechnologycanbeusedforavarietyofapplicationsincludingmotorcontrol,temperaturecontrolandpressurecontrolandsoon.InthemotorcontrolsystemshownasFig.I.,throughadjustingthedutycycleofpowerswitch,thespeedofmotorcanbecontrolled.AsshowninFig.II,underthecontrolofPWMsignal,theaverageofvoltagethatcontrolsthespeedofmotorchangeswithDuty-cycle(D=tI./TinthisFigure),thusthemotorspeedcanbeincreasedwhenmotorpowerturnon,decreasedwhenpowerturnoff.
Fig.I.:TheRelationshipbetweenVoltageofArmatureandFig.IIArchitectureofPWMModule
Therefore,themotorspeedcanbecontrolledwithregularlyadjustingthetimeofturn-onandturn-off.Therearethreemethodscouldachievetheadjustmentofdutycycle:(I.)Adjustfrequencywithfixedpulse-width.(II)Adjustbothfrequencyandpulse-width.(III)Adjustpulse-widthwithfixedfrequency.
Generally,therearefourmethodstogeneratethePWMsignalsasthefollowing:(I.)Generatedbythedevicecomposedofseparatelogiccomponents.Thismethodistheoriginalmethodwhichnowhasbeendiscarded.(II)Generatedbysoftware.ThismethodneedCPUtocontinuouslyoperateinstructionstocontrolI/OpinsforgeneratingPWMoutputsignals,sothatCPUcannotdoanythingother.Therefore,themethodalsohasbeendiscardedgradually.(III)GeneratedbyASIC.TheASICmakesadecreaseofCPUburdenandsteadyworkgenerallyhasseveralfunctionssuchasover-currentprotection,dead-timeadjustmentandsoon.Thenthemethodhasbeenwidelyusedinmanykindsofoccasionnow.(IV)GeneratedbyPWMfunctionmoduleofMCU.ThroughembeddingPWMfunctionmoduleinMCUandinitializingthefunction,PWMpinsofMCUcanalsoautomaticallygeneratePWMoutsignalswithoutCPUcontrollingonlywhenneedtochangeduty-cycle.Itisthemethodthatwillbeimplementedinthispaper.
Inthispaper,weproposeaPWMmoduleembeddedinaVIII0VIImicrocontroller.ThePWMmodulecansupportPWMpulsesignalsbyinitializingthecontrolregisterandduty-cycleregisterwiththreemethodsjustmentionedabovetoadjustthedutycycleandseveraloperationmodestoaddflexibilityforuser.
ThefollowingsectionexplainsthearchitectureofthePWMmoduleandthearchitecturesofbasicfunctionalblocks.SectionIIIdescribestwooperationmodes.Experimentalandsimulationresultsverifyingpropersystemoperationarealsoshowninthatsection.Dependingonmodeofoperation,thePWMmodulecreatesoneormorepulse-widthmodulatedsignals,whosedutyratioscanbeindependentlyadjusted.
ImplementationofPWMmoduleinMCU
OverviewofthePWMmodule
AblockdiagramofPWMmoduleisshowninFig.III.Itisclearlyfromthediagramthatthewholemoduleiscomposedoftwosections:PWMsignalgeneratoranddead-timegeneratorwithchannelselectlogic.ThePWMfunctioncanbestartedbytheuserthroughimplementingsomeinstructionsforinitializingthePWMmodule.Inparticular,thefollowingpowerandmotioncontrolapplicationsaresupported:
?DCMotor
?UninterruptablelPowerSupply(UPS)
·ThePWMmodulealsohasthefollowingfeatures:
?TwoPWMsignaloutputswithcomplementaryorindependentoperation
?Hardwaredead-timegeneratorsforcomplementarymode
?DutycycleupdatesareconfigurabletobeimmediatedorsynchronizedtothePWM
Fig.IIIArchitectureofPWMModule
Detailsofthearchitecture
PMWgenerator
ThearchitectureoftheII-outputPWMgeneratorshowninFig.IVisbasedonaI.VI-bitresolutioncounterwhichcreatesapulse-widthmodulatedsignal.ThesystemissynthesizedbyasystemclocksignalwhosefrequencycanbedividedbyIVtimesorI.IItimesthroughsettingthevalueofTIIIMforPWM0orTIVMforPWMI.inthespecialregisterPWMCONasshowninFig.IV.ToPWM0generator,theclocktoI.VI-bitcounterwillbepre-dividedbyIVtimesbydefaultwhenTIIIMissettozero.AndtheclockwillbedividedbyI.IItimeswhenTIIIMissettoI..ThisisalsotrueforPWMI..TheotherbitsinPWMCONareexplainedindetailinTableI..
Fig.IVBitMappingofPWMCON
TableI.:TheBitDefinitioninPWMCON
Channel-selectlogic
ThefollowFig.Vshowsthechannel-selectlogicwhichisusefulinComplementaryMode.Fromthisdiagram,itiscleartoknowthatsignalCPandCPWMcontrolthesourceofPWMHandPWML.AndthedetailsaboutthetwocontrolsignalswillbediscussedinthesectionIII,andthearchitectureofdead-timegeneratorwillalsobediscussedinsectionVforthecontinuityofComplementaryMode.
Fig.VDiagramofChannel-selectLogic
OperationModeandSimulationResults
Thedesignhastwooperationmodes:IndependentModeandComplimentaryMode.BysettingthecorrespondingbitCPWMinregisterPWMCONshowninFig.VIusercanselectoneofthetwooperationmodes.WhenCPWMissettozero,PWMmodulewillworkinIndependentMode,whereas,PWMmodulewillworkinComplimentaryMode.Inthefollowingofthissection,thetwooperationmodewillbeexplainedrespectivelyindetailandthesimulationresultsofthePWMmodulefromtheSynoposysVCSEDAplatformwhichverifythedesignwillalsobeshown.
IndependentPWMOutputMode
AnIndependentPWMOutputmodeisusefulfordrivingloadssuchastheoneshowninFigureVI.AparticularPWMoutputisintheIndependentOutputmodewhenthecorrespondingCPbitinthePWMCONregisterissettozero.Inthiscase,two-channelPWMoutputsareindependentofeachother.ThesignalonpinPWM0/PWMHisfromPWM0generator,andthesignalonpinPWMI./PWMLisfromPWM0generator.Theseparatecaseisachievedbythechannel-selectlogicshowninFig.VI.ThePWMI/Opinsaresettoindependentmodebydefaultuponadvicereset.Thedead-timegeneratorisdisabledintheIndependentmode.ThesimulationresultisshowninFigureVIasthefollowingFig.VITrIVandtrIIIarerunbitstoPWM0andPWMI.,respectively.Actually,fromthisdiagram,PinPI.[V]/PI.[IV]ofMCUisusedforPWMH/PWMLornormalI/O,alternatively.
FigVItheWaveformofPWMOutputsinIndependentMode
ComplementaryPWMOutputMode
TheComplementaryOutputmodeisusedtodriveinverterloadssimilartotheoneshowninFigureVII.ThisinvertertopologyistypicalforDCapplications.InComplementaryOutputMode,thepairofPWMoutputscannotbeactivesimultaneously.ThePWMchannelandoutputpinpairareinternallyconfiguredthroughchannel-selectlogicasshowninFigureVII.Adead-timemaybeoptionallyinsertedduringdeviceswitchingwherebothoutputsareinactiveforashortperiod.
FigVII:TypicalLoadforComplementaryPWMOutputs
TheComplementarymodeisselectedforPWMI/OpinpairbysettingtheappropriateCPWMbitinPWMCON.Inthiscase,PSELisineffect.PWMHandPWMLwillcomefromPWM0generatorwhenPSELissettozero,whenthesignalsfromPWMI.generatorisuseless,whereasPWMHandPWMLwillcomefromPWMI.generatorwhenPSELissettoI.,whenthesignalsfromPWM0generatorisuseless.IntheprocessofproducingthePWMoutputsinComplementaryMode,thedead-timewillbeinsertedtobediscussedinthefollowingsection.
Dead-timeControl
Dead-timegenerationisautomaticallyenabledwhenPWMI/OpinpairisoperatingintheComplementaryOutputmode.Becausethepoweroutputdevicescannotswitchinstantaneously,someamountoftimemustbeprovidedbetweentheturn-offeventofonePWMoutputinacomplementarypairandtheturn-oneventoftheothertransistor.TheII-outputPWMmodulehasoneprogrammabledead-timewithVIII-bitregister.ThecomplementaryoutputpairforthePWMmodulehasanVIII-bitdowncounterthatisusedtoproducethedead-timeinsertion.AsshowninFigureVIII,thedeadtimeunithasarisingandfallingedgedetectorconnectedtoPWMsignalfromoneofPWMgenerator.ThedeadtimesisloadedintothetimeronthedetectedPWMedgeevent.Dependingonwhethertheedgeisrisingorfalling,oneofthetransitionsonthecomplementaryoutputsisdelayeduntilthetimercountsdowntozero.AtimingdiagramindicatingthedeadtimeinsertionforthepairofPWMoutputsisshowninFigureVIIIa.
FigVIIIaDead-timeUnitBlockDiagram
Fig.VIIIbtheWaveformsofPWMOutputsinComplementaryMode
TheATVIIIIXSVIIisalow-power,high-performanceCMOSVIII-bitmicrocontrollerwithVIIIKbytesofin-systemprogrammableFlashmemory.ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindus-try-standardVIII0CVI.instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememorypro-grammer.BycombiningaversatileVIII-bitCPUwithin-systemprogrammableFlashonamonolithicchip,theAtmelATVIIIIXSVIIisapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.TheATVIIIIXSVIIprovidesthefollowingstandardfeatures:VIIIKbytesofFlash,IIVVIbytesofRAM,IIIIII/Olines,Watchdogtimer,twodatapointers,threeI.VI-bittimer/counters,asix-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theATVIIIIXSVIIisdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcon-tentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextinterruptorhardwarereset.
PinDescription
VCC:Supplyvoltage.
GND:Ground.
Port0:Port0isanVIII-bitopendrainbidirectionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.WhenI.sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpull-ups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesdur-ingprogramverification.Externalpull-upsarerequiredduringprogramverification.
PortI.:PortI.isanVIII-bitbidirectionalI/Oportwithinternalpull-ups.ThePortI.outputbufferscansink/sourcefourTTLinputs.WhenI.sarewrittentoPortI.pins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,PortI.pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Inaddition,PI..0andPI..I.canbeconfiguredtobethetimer/counterIIexternalcountinput(PI..0/TII)andthetimer/counterIItriggerinput(PI..I./TIIEX),respectively,asshowninthefollow-ingtableI..PortI.alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.
TableI.ThesecondfunctionofthePI.port
PortPinAlternateFunctions
PI..0TII(externalcountinputtoTimer/CounterII),clock-out
PI..I.TIIEX(Timer/CounterIIcapture/reloadtriggeranddirectioncontrol)
PI..VMOSI(usedforIn-SystemProgramming)
PI..VIMISO(usedforIn-SystemProgramming)
PI..VIISCK(usedforIn-SystemProgramming)
PortII:PortIIisanVIII-bitbidirectionalI/Oportwithinternalpull-ups.ThePortIIoutputbufferscansink/sourcefourTTLinputs.WhenI.sarewrittentoPortIIpins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,PortIIpinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.PortIIemitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryanddur-ingaccessestoexternaldatamemorythatuseI.VI-bitaddresses(MOVX@DPTR).Inthisapplication,PortIIusesstronginternalpull-upswhenemittingI.s.DuringaccessestoexternaldatamemorythatuseVIII-bitaddresses(MOVX@RI),PortIIemitsthecontentsofthePIISpecialFunctionRegister.PortIIalsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogram-mingandverification.
PortIII:PortIIIisanVIII-bitbidirectionalI/Oportwithinternalpull-ups.ThePortIIIoutputbufferscansink/sourcefourTTLinputs.WhenI.sarewrittentoPortIIIpins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,PortIIIpinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepull-ups.PortIIIreceivessomecontrolsignalsforFlashprogrammingandverification.PortIIIalsoservesthefunctionsofvariousspecialfeaturesoftheATVIIIIXSVII,asshowninthefol-lowingtableII.
TableIIThesecondfunctionofthePIIIport
PortPinAlternateFunctions
PIII.0RXD(serialinputport)
PIII.I.TXD(serialoutputport)
PIII.II(externalinterrupt0)
PIII.III(externalinterruptI.)
PIII.IVT0(timer0externalinput)
PIII.VTI.(timerI.externalinput)
PIII.VI(externaldatamemorywritestrobe)
PIII.VII(externaldatamemoryreadstrobe)
RST:Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.ThispindriveshighforIXVIIIoscillatorperiodsaftertheWatchdogtimesout.TheDISRTObitinSFRAUXR(addressVIIIEH)canbeusedtodisablethisfeature.InthedefaultstateofbitDISRTO,theRESETHIGHoutfeatureisenabled.
ALE/:AddressLatchEnable(ALE)isanoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput()duringFlashprogramming.Innormaloperation,ALEisemittedataconstantrateofI./VItheoscillatorfrequencyandmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippeddur-ingeachaccesstoexternaldatamemory.Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocationVIIIEH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.
:ProgramStoreEnable()isthereadstrobetoexternalprogrammemory.WhentheATVIIIIXSVIIisexecutingcodefromexternalprogrammemory,isactivatedtwiceeachmachinecycle,exceptthattwoactivationsareskippedduringeachaccesstoexter-naldatamemory.
/VPP:ExternalAccessEnable.mustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbitI.isprogrammed,willbeinternallylatchedonreset.shouldbestrappedtoVCCforinternalprogramexecutions.ThispinalsoreceivestheI.II-voltprogrammingenablevoltage(VPP)duringFlashprogramming.
XTALI.:Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.
XTALII:Outputfromtheinvertingoscillatoramplifier.
ProgramMemory
IfthepinisconnectedtoGND,allprogramfetchesaredirectedtoexternalmemory.OntheATVIIIIXSVII,ifisconnectedtoVCC,programfetchestoaddresses0000HthroughI.FFFHaredirectedtointernalmemoryandfetchestoaddressesII000HthroughFFFFHaretoexternalmemory.
DataMemory
TheATVIIIIXSVIIimplementsIIVVIbytesofon-chipRAM.TheupperI.IIVIIIbytesoccupyaparalleladdressspacetotheSpecialFunctionRegisters.ThismeansthattheupperI.IIVIIIbyteshavethesameaddressesastheSFRspacebutarephysicallyseparatefromSFRspace.WhenaninstructionaccessesaninternallocationaboveaddressVIIFH,theaddressmodeusedintheinstructionspecifieswhethertheCPUaccessestheupperI.IIVIIIbytesofRAMortheSFRspace.InstructionswhichusedirectaddressingaccesstheSFRspace.Forexample,thefollowingdirectaddressinginstructionaccessestheSFRatlocation0A0H(whichisPII).MOV0A0H,#data.InstructionsthatuseindirectaddressingaccesstheupperI.IIVIIIbytesofRAM.Forexample,thefollowingindirectaddressinginstruction,whereR0contains0A0H,accessesthedatabyteataddress0A0H,ratherthanPII(whoseaddressis0A0H).MOV@R0,#data.Notethatstackoperationsareexamplesofindirectaddressing,sotheupperI.IIVIIIbytesofdataRAMareavailableasstackspace.
WatchdogTimer
TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsets.TheWDTconsistsofaI.IV-bitcounterandtheWatchdogTimerReset(WDTRST)SFR.TheWDTisdefaultedtodisablefromexitingreset.ToenabletheWDT,ausermustwrite0I.EHand0EI.HinsequencetotheWDTRSTregister(SFRlocation0AVIH).WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.TheWDTtimeoutperiodisdependentontheexternalclockfrequency.ThereisnowaytodisabletheWDTexceptthroughreset(eitherhardwareresetorWDToverflowreset).WhenWDTover-flows,itwilldriveanoutputRESETHIGHpulseattheRSTpin.
InPower-downmodetheoscillatorstops,whichmeanstheWDTalsostops.WhileinPower-downmode,theuserdoesnotneedtoservicetheWDT.TherearetwomethodsofexitingPower-downmode:byahardwareresetorviaalevel-activatedexternalinterruptwhichisenabledpriortoenteringPower-downmode.WhenPower-downisexitedwithhardwarereset,servicingtheWDTshouldoccurasitnormallydoeswhenevertheATVIIIIXSVIIisreset.ExitingPower-downwithaninterruptissignificantlydifferent.Theinterruptisheldlowlongenoughfortheoscillatortostabilize.Whentheinterruptisbroughthigh,theinterruptisserviced.TopreventtheWDTfromresettingthedevicewhiletheinterruptpinisheldlow,theWDTisnotstarteduntiltheinterruptispulledhigh.ItissuggestedthattheWDTberesetduringtheinterruptservicefortheinterruptusedtoexitPower-downmode.ToensurethattheWDTdoesnotoverflowwithinafewstatesofexitingPower-down,itisbesttoresettheWDTjustbeforeenteringPower-downmode.BeforegoingintotheIDLEmode,theWDIDLEbitinSFRAUXRisusedtodeterminewhethertheWDTcontinuestocountifenabled.TheWDTkeepscountingduringIDLE(WDIDLEbit=0)asthedefaultstate.TopreventtheWDTfromresettingtheATVIIIIXSVIIwhileinIDLEmode,theusershouldalwayssetupatimerthatwillperiodicallyexitIDLE,servicetheWDT,andreenterIDLEmode.WithWDIDLEbitenabled,theWDTwillstoptocountinIDLEmodeandresumesthecountuponexitfromIDLE.
Timer0andI.
Timer0andTimerI.intheATVIIIIXSVIIoperatethesamewayasTimer0andTimerI.intheATVIIIIXCVI.andATVIIIIXCVII.Forfurtherinformationonthetimers’operation,pleaseclickonthedocumentlinkbelow:
http://www.atmel.com/dyn/resources/prod_documents/DOCIVIIII.VI.PDF
TimerII
TimerIIisaI.VI-bitTimer/Counterthatcanoperateaseitheratimeroraneventcounter.ThetypeofoperationisselectedbybitC/intheSFRTIICON.TimerIIhasthreeoperatingmodes:capture,auto-reload(upordowncounting),andbaudrategenerator.ThemodesareselectedbybitsinTIICON,asshowninTableVI-I..TimerIIconsistsoftwoVIII-bitregisters,THIIandTLII.IntheTimerfunction,theTLIIregisterisincrementedeverymachinecycle.SinceamachinecycleconsistsofI.IIoscillatorperiods,thecountrateisI./I.IIoftheoscil-latorfrequency.
TableIIITimerIIOperatingModes
RCLK+TCLKCP/TRIIMODE
00I.I.VI-bitAuto-reload
0I.I.I.VI-bitCapture
I.XI.BaudRateGenerator
XX0(Off)
IntheCounterfunction,theregisterisincrementedinresponsetoaI.-to-0transitionatitscorre-spondingexternalinputpin,TII.Inthisfunction,theexternalinputissampledduringSVPIIofeverymachinecycle.Whenthesamplesshowahighinonecycleandalowinthenextcycle,thecountisincremented.ThenewcountvalueappearsintheregisterduringSIIIPI.ofthecyclefollowingtheoneinwhichthetransitionwasdetected.Sincetwomachinecycles(IIIVoscillatorperiods)arerequiredtorecognizeaI.-to-0transition,themaximumcountrateisI./IIIVoftheoscillatorfrequency.Toensurethatagivenlevelissampledatleastoncebeforeitchanges,thelevelshouldbeheldforatleastonefullmachinecycle.
Interrupts
TheATVIIIIXSVIIhasatotalofsixinterruptvectors:twoexternalinterrupts(and),threetimerinterrupts(Timers0,I.,andII),andtheserialportinterrupt.EachoftheseinterruptsourcescanbeindividuallyenabledordisabledbysettingorclearingabitinSpecialFunctionRegisterIE.IEalsocontainsaglobaldisablebit,EA,whichdisablesallinterruptsatonce.NotethatbitpositionIE.VIisunimplemented.UsersoftwareshouldnotwriteaI.tothisbitposition,sinceitmaybeusedinfutureATVIIIIXproducts.TimerIIinterruptisgeneratedbythelogicalORofbitsTFIIandEXFIIinregisterTIICON.Nei-theroftheseflagsisclearedbyhardwarewhentheserviceroutineisvectoredto.Infact,theserviceroutinemayhavetodeterminewhetheritwasTFIIorEXFIIthatgeneratedtheinterrupt,andthatbitwillhavetobeclearedinsoftware.TheTimer0andTimerI.flags,TF0andTFI.,aresetatSVPIIofthecycleinwhichthetimersoverflow.Thevaluesarethenpolledbythecircuitryinthenextcycle.However,theTimerIIflag,TFII,issetatSIIPIIandispolledinthesamecycleinwhichthetimeroverflows.
OscillatorCharacteristics
XTALI.andXTALIIaretheinputandoutput,respectively,ofaninvertingamplifierthatcanbeconfiguredforuseasanon-chiposcillator.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTALIIshouldbeleftunconnectedwhileXTALI.isdriven,.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclock-ingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.
Power-downMode
InthePower-downmode,theoscillatorisstopped,andtheinstructionthatinvokesPower-downisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthePower-downmodeisterminated.ExitfromPower-downmodecanbeinitiatedeitherbyahardwareresetorbyanenabledexternalinterrupt.ResetredefinestheSFRsbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.
IdleMod
Inidlemode,theCPUputsitselftosleepwhilealltheon-chipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregis-tersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.Notethatwhenidlemodeisterminatedbyahardwarereset,thedevicenormallyresumespro-gramexecutionfromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.Toeliminatethepossibilityofanunexpectedwritetoaportpinwhenidlemodeisterminatedbyareset,theinstructionfollowingtheonethatinvokesidlemodeshouldnotwritetoaportpinortoexternalmemory.
Conclusions
Inthispaper,wehavedesignedPWMmodulebasedonanVIII-bitMCUcompatiblewithVIII0VIIfamily.ThedesigncangenerateII-channelprogrammableperiodicPWMsignalswithtwooperationmode,IndependentModeandComplementaryModeinwhichdead-timewillbeinserted.ThesimulationresultsontheEDAplatformhaveprovenitscorrectnessandusefulness.
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